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Title: A 1.7mW 11b 1-1-1 MASH Delta-Sigma Time-to-Digital Converter
Author(s): Cao, Ying
Leroux, Paul
De Cock, Wouter
Steyaert, Michiel
Keywords: MYRRHA
MASH Delta-Sigma Time-to-Digital Converter
Issue Date: 24-Feb-2011
Publication type: In-proceedings paper
Citation: Cao Y., Leroux P., De Cock W., Steyaert M.- A 1.7mW 11b 1-1-1 MASH Delta-Sigma Time-to-Digital Converter.- In: IEEE 2011 International Solid-State Circuits Conference Digest of Technical Papers, San-Francisco, United States, 20-24 February 2011 / IEEE, United States, IEEE, 2011
Abstract: Recently, high resolution TDCs have gained more and more interest due to their increasing implementation in digital PLLs, ADCs, jitter measurement and time-of-flight measurement units. Similar to ADCs, existing architectures of TDCs can be divided into several categories: flash TDCs [1,3], pipeline TDCs [2], and SAR TDCs [4]. The highest achievable time resolution of a TDC is mainly limited by the CMOS gate delay. In order to get sub-gate-delay resolution, the Vernier method is commonly used. However, the mismatch problem caused by process variation limits its effectiveness, and the same holds for the time amplification method. The gated-ring-oscillator (GRO) method [5] is introduced to achieve sub-ps time resolution, but it still requires an equivalent CMOS gate delay as low as 6ps. Upcoming applications in 4th generation nuclear reactors, space and high energy physics like the Large Hadron Collider (LHC), require the TDC to achieve a high time resolution in harsh environments with high temperature and radiation, where the threshold voltage, transconductance, and delay of a transistor undergo dramatic changes. In these cases, the high accuracy and robustness of the TDC need to be inherent to the design rather than by employing a fast CMOS technology.
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