A 1.7mW 11b 1-1-1 MASH Delta-Sigma Time-to-Digital Converter

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Standard

A 1.7mW 11b 1-1-1 MASH Delta-Sigma Time-to-Digital Converter. / Cao, Ying; Leroux, Paul; De Cock, Wouter; Steyaert, Michiel; Vermeeren, Ludo (Peer reviewer).

IEEE 2011 International Solid-State Circuits Conference Digest of Technical Papers. United States, 2011.

Research output: Contribution to report/book/conference proceedingsIn-proceedings paperpeer-review

Harvard

Cao, Y, Leroux, P, De Cock, W, Steyaert, M & Vermeeren, L 2011, A 1.7mW 11b 1-1-1 MASH Delta-Sigma Time-to-Digital Converter. in IEEE 2011 International Solid-State Circuits Conference Digest of Technical Papers. United States, ISSCC 2011 - International Solid State Circuits Conference, San-Francisco, United States, 2011-02-20.

APA

Cao, Y., Leroux, P., De Cock, W., Steyaert, M., & Vermeeren, L. (2011). A 1.7mW 11b 1-1-1 MASH Delta-Sigma Time-to-Digital Converter. In IEEE 2011 International Solid-State Circuits Conference Digest of Technical Papers

Vancouver

Cao Y, Leroux P, De Cock W, Steyaert M, Vermeeren L. A 1.7mW 11b 1-1-1 MASH Delta-Sigma Time-to-Digital Converter. In IEEE 2011 International Solid-State Circuits Conference Digest of Technical Papers. United States. 2011

Author

Cao, Ying ; Leroux, Paul ; De Cock, Wouter ; Steyaert, Michiel ; Vermeeren, Ludo. / A 1.7mW 11b 1-1-1 MASH Delta-Sigma Time-to-Digital Converter. IEEE 2011 International Solid-State Circuits Conference Digest of Technical Papers. United States, 2011.

Bibtex - Download

@inproceedings{ae69c256003049639b29ec7f2cd0c030,
title = "A 1.7mW 11b 1-1-1 MASH Delta-Sigma Time-to-Digital Converter",
abstract = "Recently, high resolution TDCs have gained more and more interest due to their increasing implementation in digital PLLs, ADCs, jitter measurement and time-of-flight measurement units. Similar to ADCs, existing architectures of TDCs can be divided into several categories: flash TDCs [1,3], pipeline TDCs [2], and SAR TDCs [4]. The highest achievable time resolution of a TDC is mainly limited by the CMOS gate delay. In order to get sub-gate-delay resolution, the Vernier method is commonly used. However, the mismatch problem caused by process variation limits its effectiveness, and the same holds for the time amplification method. The gated-ring-oscillator (GRO) method [5] is introduced to achieve sub-ps time resolution, but it still requires an equivalent CMOS gate delay as low as 6ps. Upcoming applications in 4th generation nuclear reactors, space and high energy physics like the Large Hadron Collider (LHC), require the TDC to achieve a high time resolution in harsh environments with high temperature and radiation, where the threshold voltage, transconductance, and delay of a transistor undergo dramatic changes. In these cases, the high accuracy and robustness of the TDC need to be inherent to the design rather than by employing a fast CMOS technology.",
keywords = "MYRRHA, LIDAR, CMOS, MASH Delta-Sigma Time-to-Digital Converter",
author = "Ying Cao and Paul Leroux and {De Cock}, Wouter and Michiel Steyaert and Ludo Vermeeren",
note = "Score = 3; ISSCC 2011 - International Solid State Circuits Conference ; Conference date: 20-02-2011 Through 24-02-2011",
year = "2011",
month = feb,
day = "24",
language = "English",
booktitle = "IEEE 2011 International Solid-State Circuits Conference Digest of Technical Papers",

}

RIS - Download

TY - GEN

T1 - A 1.7mW 11b 1-1-1 MASH Delta-Sigma Time-to-Digital Converter

AU - Cao, Ying

AU - Leroux, Paul

AU - De Cock, Wouter

AU - Steyaert, Michiel

A2 - Vermeeren, Ludo

N1 - Score = 3

PY - 2011/2/24

Y1 - 2011/2/24

N2 - Recently, high resolution TDCs have gained more and more interest due to their increasing implementation in digital PLLs, ADCs, jitter measurement and time-of-flight measurement units. Similar to ADCs, existing architectures of TDCs can be divided into several categories: flash TDCs [1,3], pipeline TDCs [2], and SAR TDCs [4]. The highest achievable time resolution of a TDC is mainly limited by the CMOS gate delay. In order to get sub-gate-delay resolution, the Vernier method is commonly used. However, the mismatch problem caused by process variation limits its effectiveness, and the same holds for the time amplification method. The gated-ring-oscillator (GRO) method [5] is introduced to achieve sub-ps time resolution, but it still requires an equivalent CMOS gate delay as low as 6ps. Upcoming applications in 4th generation nuclear reactors, space and high energy physics like the Large Hadron Collider (LHC), require the TDC to achieve a high time resolution in harsh environments with high temperature and radiation, where the threshold voltage, transconductance, and delay of a transistor undergo dramatic changes. In these cases, the high accuracy and robustness of the TDC need to be inherent to the design rather than by employing a fast CMOS technology.

AB - Recently, high resolution TDCs have gained more and more interest due to their increasing implementation in digital PLLs, ADCs, jitter measurement and time-of-flight measurement units. Similar to ADCs, existing architectures of TDCs can be divided into several categories: flash TDCs [1,3], pipeline TDCs [2], and SAR TDCs [4]. The highest achievable time resolution of a TDC is mainly limited by the CMOS gate delay. In order to get sub-gate-delay resolution, the Vernier method is commonly used. However, the mismatch problem caused by process variation limits its effectiveness, and the same holds for the time amplification method. The gated-ring-oscillator (GRO) method [5] is introduced to achieve sub-ps time resolution, but it still requires an equivalent CMOS gate delay as low as 6ps. Upcoming applications in 4th generation nuclear reactors, space and high energy physics like the Large Hadron Collider (LHC), require the TDC to achieve a high time resolution in harsh environments with high temperature and radiation, where the threshold voltage, transconductance, and delay of a transistor undergo dramatic changes. In these cases, the high accuracy and robustness of the TDC need to be inherent to the design rather than by employing a fast CMOS technology.

KW - MYRRHA

KW - LIDAR

KW - CMOS

KW - MASH Delta-Sigma Time-to-Digital Converter

UR - http://ecm.sckcen.be/OTCS/llisapi.dll/open/ezp_112250

UR - http://ecm.sckcen.be/OTCS/llisapi.dll/open/ezp_112250_2

UR - http://knowledgecentre.sckcen.be/so2/bibref/7855

M3 - In-proceedings paper

BT - IEEE 2011 International Solid-State Circuits Conference Digest of Technical Papers

CY - United States

T2 - ISSCC 2011 - International Solid State Circuits Conference

Y2 - 20 February 2011 through 24 February 2011

ER -

ID: 324075