Abstract
Strain engineering based on either a global approach using high-mobility substrates or the implementation
of so-called processing-induced stressors has become common practice for 90 nm and below CMOS
technologies. Although the main goal is to improve the performance by increasing the drive current,
other electrical parameters such as the threshold voltage, the multiplication current, the low frequency
noise and the gate oxide quality in general may be influenced. This paper reviews the impact of different
global and local strain engineering techniques on the gate stack quality and its reliability, including hot
carrier performance, negative bias temperature instabilities, time dependent dielectric breakdown and
radiation hardness. Recent insights will be discussed and the influence of different strain engineering
approaches illustrated.
Details
Original language | English |
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Pages (from-to) | 1115-1126 |
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Journal | Solid-State Electronics |
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Volume | 52 |
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Issue number | 8 |
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DOIs | |
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Publication status | Published - Aug 2008 |
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