Impact Strain Engineering on Gate Stack Quality and Reliability

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  • Cor Claeys
  • Eddy Simoen
  • Sofie Put
  • Gino Giusi
  • Felice Crupi

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Strain engineering based on either a global approach using high-mobility substrates or the implementation of so-called processing-induced stressors has become common practice for 90 nm and below CMOS technologies. Although the main goal is to improve the performance by increasing the drive current, other electrical parameters such as the threshold voltage, the multiplication current, the low frequency noise and the gate oxide quality in general may be influenced. This paper reviews the impact of different global and local strain engineering techniques on the gate stack quality and its reliability, including hot carrier performance, negative bias temperature instabilities, time dependent dielectric breakdown and radiation hardness. Recent insights will be discussed and the influence of different strain engineering approaches illustrated.


Original languageEnglish
Pages (from-to)1115-1126
JournalSolid-State Electronics
Issue number8
Publication statusPublished - Aug 2008


  • Silicon-on-Insulator (SOI), Fully depleted SOI MOSFETs, LF-Noise, Strain engineering, low-field mobility, irradiation

ID: 70358